1. Field of the Invention
The present invention relates to a semiconductor device and a method of manufacturing the device, and more specifically to the improvements in the pattern configuration of an ROM region of a semiconductor device incorporating an ROM (Read Only Memory) and to a method of manufacturing the device.
2. Description of the Background Art
In general, in manufacturing a semiconductor device incorporating an ROM formed using photolithography and ion-implantation techniques, the specifications of the ROM vary according to the needs of the customers. Consequently, since all semiconductor devices employ masks of identical specifications, during the manufacturing steps of the semiconductor device incorporating an ROM, the same manufacturing steps are adopted as far as the step preceding the forming step of an ROM region. As a result, the structures of the semiconductor devices at this unfinished stage are identical, and in this unfinished condition the semiconductor devices are stored for the time being.
Then, after the specifications of an ROM are determined based on the order placed by the customer, the manufacturing steps for the unfinished semiconductor device are resumed, an ROM region is patterned according to the ROM specifications, and the final manufacturing steps are carried out.
Referring now to FIG. 14, the planar pattern structure of an ROM region in the conventional semiconductor device will be described.
Element isolating regions 12 are disposed regularly at predetermined intervals in the X and Y directions, and gate interconnection layers 13 extending in the Y direction are disposed at predetermined intervals in the X direction.
Aluminum interconnection layers 10 extending in the X direction are disposed at predetermined intervals in the Y direction in regions between element isolating regions 12. A plurality of contact holes 9 are provided in aluminum interconnection layer 10 to provide electrical connection to active regions on a semiconductor substrate 1. A channel region 14 of an ROM transistor is formed on semiconductor substrate 1 where gate interconnection layer 13 and aluminum interconnection layer 10 intersect.
Referring now to FIGS. 15-19, the manufacturing steps of an ROM transistor formed in the ROM region having the above-mentioned structure will be described below.
Referring first to FIG. 15, element isolating region 12 as shown in FIG. 14 is formed in a matrix using the LOCOS (Local Oxidation of Silicon) method to define an active region in a given region on the surface of silicon semiconductor substrate 1.
Next, a silicon oxide film 2 having a thickness of 100 xc3x85 to 300 xc3x85 is formed by thermal oxidation on the surface of silicon semiconductor substrate 1. Thereafter, a polycrystalline silicon layer 3 having a film thickness of 1000 xc3x85 to 3000 xc3x85 is formed on oxide film 2 using the CVD (Chemical Vapor Deposition) method. Then, on polycrystalline silicon layer 3, a tungsten silicide layer 4 having a film thickness of 1000 xc3x85 to 3000 xc3x85 is formed by sputtering.
Thereafter, silicon oxide film 2, polycrystalline silicon layer 3, and tungsten silicide layer 4 are patterned using photolithography and etching techniques. Thus, gate interconnection layer 13 including oxide film 2, polycrystalline silicon layer 3, and tungsten silicide layer 4 is completed.
Next, referring to FIG. 16, using as a mask the gate interconnection layer 13 including oxide film 2, polycrystalline silicon layer 3, and tungsten silicide layer 4, an n-type impurity such as As is implanted with a dosage of 1xc3x971015/cm2 to 1xc3x971016/cm2 at an implantation energy of 30 keV to 60 keV into semiconductor substrate 1. Then, the impurity implanted into semiconductor substrate 1 is diffused thermally, and n+ type impurity diffusion regions 5 which later become source/drain regions of an ROM transistor is completed.
Referring now to FIG. 17, a resist film 7 of a predetermined pattern is formed selectively on n+ type impurity diffusion region 5. Thereafter, in order to determine the threshold voltage (Vth) of the ROM transistor, p-type impurity ions 8 such as boron are implanted into channel region 14 at an acceleration voltage, for example at approximately 200 keV, which penetrates oxide film 2, polycrystalline silicon layer 3, and tungsten silicide layer 4 to form channel implant 38.
Referring now to FIG. 18, resist film 7 is removed, and then, semiconductor substrate 1 is heat-treated to activate p-type impurity ions 8. Thereafter, an interlayer insulating film 6 having a thickness of 0.4 xcexcm to 1.2 xcexcm and being formed of TEOS (Tetra Ethyl Ortho Silicate) and/or BPSG (Boro Phospho Silicate Glass) is formed by the CVD method so as to cover tungsten silicide layer 4 and n+ type impurity diffusion region 5. Then, contact hole 9 reaching n+ type impurity diffusion region 5 is formed selectively in interlayer insulating film 6 by etching.
Referring now to FIG. 19, aluminum interconnection layer 10 having a film thickness of 0.6 xcexcm to 1.0 xcexcm is formed by sputtering, and thereafter, a surface protection film 11 such as a nitride film having a film thickness of 0.5xcexcm to 1.0 xcexcm is formed by the CVD method. From the above-described steps, the ROM transistor is formed with its threshold voltage (Vth) set at a predetermined level.
The patterned structure of the aforementioned conventional ROM transistor, however, is as shown in FIG. 14 in which aluminum interconnection layer 10 crosses channel region 14 where impurity ions are implanted to determine the threshold voltage (Vth) of the ROM transistor.
Thus, the manufacturing steps are interrupted after forming n+ type impurity diffusion regions 5 which later become the source/drain regions of the ROM transistor shown in FIG. 16, and the final manufacturing steps shown in FIGS. 17-19 are performed after the ROM specifications are determined based on the order placed by the customer.
As a result, due to the long manufacturing period required for the final manufacturing steps shown in FIGS. 17-19 after the ROM specifications are determined, it has been a problem that too much time was required from the time of order to the time when the products are supplied to the customer.
An object of the present invention is to provide a semiconductor device and a method of manufacturing the device which shortens the manufacturing period required for the final manufacturing steps of a semiconductor device after the ROM specifications are determined.
A semiconductor device according to the present invention is provided with an element isolating region disposed in a matrix for defining an active region on a semiconductor substrate, first conductive layers extending in a direction and disposed at predetermined intervals from each other above the element isolating region, and second conductive layers extending in a direction intersecting the first conductive layers and disposed at predetermined intervals from each other above the first conductive layers. The second conductive layer, also, is disposed above the element isolating region.
Moreover, preferably in the above-mentioned semiconductor device, the active region forms source/drain regions and a channel region, the first conductive layer forms a gate interconnection layer, the second conductive layer forms an aluminum interconnection layer, and the source/drain regions, the channel region, the gate interconnection layer, and the aluminum interconnection layer together form an ROM transistor.
In accordance with one aspect of the method of manufacturing a semiconductor device according to the present invention, the method includes the steps of forming an element isolating region in a matrix to define an active region on a semiconductor substrate, forming a first conductive layer at a given location of the active region defined by the element isolating region with an insulating film therebetween, introducing a first impurity into the semiconductor substrate using the first conductive layer as a mask to form an impurity diffusion region, covering the impurity diffusion region and the first conductive layer to form an interlayer insulating film having a contact hole reaching to the impurity diffusion region, forming on the interlayer insulating film a second conductive layer extending above the element isolating region and connecting electrically to the impurity diffusion region at a contact hole, forming a surface protection layer covering the interlayer insulating film and the second conductive layer, forming on the surface protection layer a resist film leaving exposed a region corresponding to the active region below the first conductive layer, and introducing a second impurity into the active region using the resist film as a mask to adjust the concentration of impurity in the active region below the first conductive layer.
In the above-mentioned semiconductor device and the method of manufacturing the device, the second conductive layer is formed extending above the element isolating region. Therefore, only the first conductive layer, the interlayer insulating film, and the surface protection layer exist above the active region which forms a channel region. Consequently, it is possible to adjust the concentration of the impurity in the active region below the first conductive layer after the surface protection layer is formed.
In the aforementioned semiconductor device, the insulating film is preferably a silicon oxide film having a thickness of 100 xc3x85 to 300 xc3x85 formed by thermal oxidation. The first conductive layer has a film thickness of 2000 xc3x85 to 6000 xc3x85 and has a two-layered structure including a polycrystalline silicon layer formed by the CVD method and a tungsten silicide layer formed by sputtering. The interlayer insulating film has a thickness of 0.4 xcexcm to 1.2 xcexcm, is made of at least one of TEOS and BPSG, and is formed by the CVD method. The surface protection layer is a nitride film with a thickness of 0.5 xcexcm to 1.0 xcexcm. The second impurity is introduced at an acceleration voltage of 1000 keV to 2000 keV.
Thus, the introduction of the second impurity into the active region is ensured using the resist film as a mask.
Next, in accordance with another aspect of the method of manufacturing a semiconductor device according to the present invention, the method includes the steps of forming an element isolating region in a matrix to define an active region on a semiconductor substrate, forming a first conductive layer at a given location of the active region defined by the element isolating region with an insulating film therebetween, introducing a first impurity into the semiconductor substrate using the first conductive layer as a mask to form an impurity diffusion region, covering the impurity diffusion region and the first conductive layer to form an interlayer insulating film having a contact hole leading to the impurity diffusion region, forming a resist film covering the contact hole and leaving exposed a region corresponding to the active region below the first conductive layer, introducing a second impurity into the active region using the resist film as a mask to adjust the concentration of impurity in the active region below the first conductive layer, removing the resist film and thereafter forming on the interlayer insulating film a second conductive layer connecting electrically to the impurity diffusion region at a contact hole, and forming a surface protection layer covering the second conductive layer.
According to the method of manufacturing the semiconductor device described above, the concentration of the impurity in the active region below the first conductive layer can be adjusted after the interlayer insulating film is formed.
In the aforementioned semiconductor device, the insulating film is preferably a silicon oxide film having a thickness of 100 xc3x85 to 300 xc3x85 formed by thermal oxidation. The first conductive layer has a film thickness of 2000 xc3x85 to 6000 xc3x85 and has a two-layered structure including a polycrystalline silicon layer formed by the CVD method and a tungsten silicide layer formed by sputtering. The interlayer insulating film has a film thickness of 0.4 xcexcm to 1.2 xcexcm, is made of at least one of TEOS and BPSG, and is formed by the CVD method. The second impurity is introduced at an acceleration voltage of 400 keV to 1000 keV.
Thus, the introduction of the second impurity into the active region is ensured using the resist film as a mask.
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.